The design flow of an integrated circuit (IC) includes several stages. One of the stages is an electrostatic discharge (ESD) analysis stage, during which simulation of ESD circuitry of the integrated circuit is performed. Typically, the ESD analysis stage occurs toward the end of the design flow, after the circuit schematic and physical layout designs of the entire integrated circuit are finished and right before tapeout. It is performed toward the end because it uses the layout of the IC to perform the analysis.
The ESD analysis stage may determine ESD performance characteristics of the ESD circuitry. Because the ESD analysis stage is performed toward the end of the design flow, then if the ESD analysis stage identifies ESD performance characteristics that are unsatisfactory, redesign of the IC in order to improve ESD performance characteristics may set back the design flow schedule on the order of months. Alternatively, risk with regard to ESD performance and robustness is assumed if the schedule cannot be delayed. In order to guard against the undesirable effects of the ESD analysis stage identifying unsatisfactory performance characteristics, the ESD circuitry may be designed with a large amount of pessimism, meaning that the ESD circuitry may be over designed or designed with extra margin, such as by designing it with extra area or with extra rails in order to aim for a lower than expected rail or path resistance. Accordingly, it may be desirable to implement a design flow that allows for optimizing the design of the ESD circuitry without disrupting the design flow schedule.